1. Field of the Invention
This invention relates to semiconductor data storage devices and, more specifically, to a high performance fault tolerant orthogonal shuffle memory.
2. Statement of the Prior Art
As will be known to those skilled in the art, large capacity semiconductor data storage devices with sequential, parallel-sequential, random-sequential, and associative-sequential access modes have been implemented by means of random access memories (RAMs) coupled to an address sequencer device, or by means of a shift register (SR) type of device. Fault tolerancy for RAMs has been provided by implementation of bidirectional single parity check codes or Hamming codes, and by using redundant elements for replacements of faulty rows, columns or subarrays. Fault tolerancy for SRs and SR type of devices has been provided by the application of cyclic Hamming or some other digital cyclic codes or by duplications or by triplication of the device.
The conventional RAM approach, in configurations which involve implementations of sequential write, read or transfer of data, provide relatively low delta rates, high power dissipation, low reliability, low radiation hardness, low immunity against impacts of atomic particles, low tolerance for temperature variation, high noise sensitivity and high manufacturing costs in comparison to logic circuits fabricated with the same processing technology. The conventional RAM approach comprises arrays of memory cells, sense amplifiers, decoders, buffers, controllers and auxiliary address sequencers. In this configuration, the data rate for sequential write, read and transfer is limited by the access and cycle times of the RAM.
In RAM approaches, each datum is addressed separately through a critical time delay path which traditionally includes the additive delays produced by an address sequencer, a decoder, bus lines in the array of memory cells, sense amplifiers, buffers and an eventual error detector and corrector. Furthermore, the conventional RAM operation consumes a high amount of power, because at each access, all data lines and data terminals of the memory cells are precharged, while at least a cluster of sense amplifiers, the entire decoder, all input and output buffers, the controller, and the error detector and corrector are simultaneously activated. Moreover, the conventional RAMs are plagued with low reliability, little tolerance for the effects of accumulative ionizing radiation, temperature variations, and electromagnetic noises, because of the array-inherent small signal and data sensing operation.
In a RAM array, an address memory cell is loaded by a large impedance that includes the parasitic capacitance of the data line, the input capacitances of all unaddressed cells and the sense amplifier which is connected to the data line, as well as the resistances of said data line and the access device of the addressed cell. This large load impedance allows only very slow changes in read signal amplitudes which are accelerated and amplified by sense amplifiers. The sense amplifiers are of differential types in which any little imbalance may impair the operation. Imbalances in differential amplifiers are results of non-symmetrical change in transistor and interconnect parameters. These parameters may be degraded by the effect of semiconductor processing, nuclear irradiation, hot electron emission, temperature variations and others. The small signal type of operation allows for little operational margins which may disappear at small changes in transistor and interconnect parameters. Furthermore, data stored in traditional RAM cells may easily be altered by impacts of alpha or other atomic particles emitted from semiconductor packaging or present in cosmic environments. The manufacturing costs of traditional RAMs are high because of the tight parameter control and extra processing steps required for the circuits operating with small signals and for minimizing the sizes of memory cells.
The traditional SRs and SR-like devices dissipate excessive amount of power and are implemented in packing densities which are uncompetitive with RAMs for mass storage applications. The conventional SR approach comprises shift register stages, buffers and a controller. In this approach, the power dissipation is prohibitively high to implement large arrays, because at write, read and transfer operations, all register stages are simultaneously activated. Furthermore, SRs of dynamic types have to continuously rotate and amplify data content in order to avoid data losses. Moreover, the packing density of SRs is inherently low, because each of the register states comprises at least two data storage elements and two data transmission elements. This is in contrast to RAM cells which comprise only one data storage element and one or two data transmission elements.
The conventional error detectors and correctors, which have been implemented in cooperation with RAMs on a single semiconductor body, are capable of correcting only single bit errors and, in some designs, double bit errors, so as to considerably degrade the performance parameters of the RAMs. The most frequently implemented bidirectional single parity and imparity check code can correct only single bit errors. The speed and power performances of the RAM degrades considerably due to the circuit implementation of bidirectional single parity and imparity check codes and because traditional approaches use a large amount of two and three input logic gates in chain and parallel connections.
The rarely implemented double error correcting Hamming code needs a considerable amount of redundant bits for the increase of error correcting. SRs and SR type of storage devices use mostly cyclic Hamming codes for error detection and corrections thereby providing less degradation in speed and power than Hamming codes do in RAMs. Small SRs have occasionally been duplicated or triplicated to provide fault tolerancy, but such redundancy results in decreased packing density and increased power consumption.